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-- Company: 
-- Engineer: 
-- 
-- Create Date:    16:08:47 03/25/2011 
-- Design Name: 
-- Module Name:    Mult2_1W - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library work;
use work.Definitions.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity Mult_W is
    Port ( dataw 		: in  data_word_type;
           accw 		: in  data_word_type;
			  is_in 		: in STD_LOGIC;
           is_load 	: in  STD_LOGIC;
           outputw 	: out  std_logic_vector (7 downto 0));
end Mult_W;

architecture Behavioral of Mult_W is

begin
process(dataw, accw, is_in, is_load) is
begin
	case is_in or is_load is
		when '0' => outputw <= accw;
		when others =>  outputw <= dataw;
	end case;
end process;
end Behavioral;

